High speed data conversion& signal processing solutions

Real time processing Electronic Warfare Radar receiver

Kintex UltraScale FPGA
Dual FMC carrier
Quad 16-bit 2.5Gsps DAC

  • 2 FMC-HPC slots
  • 1 channel 16-bit 370Msps ADC
  • 2 channels 16-bit 2.5Gsps DAC
  • One Ultra Low jitter clock synthesizers
  • External or internal sampling clock
  • Internal sampling clock reference
  • 12 Tx and 12 Rx fiber interface supporting up to 14Gbps
  • User programmable Xilinx® Kintex® Ultrascale™ KU115 FPGA
  • 800 MHz 1x 256M32 DDR3 SDRAM
  • Air cooled rugged version


  • FGPA Processing
  • Communication


  • Radar Receiver
  • Electronic Warfare


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The AS103 is part of ApisSys' range of High Speed data conversion and signal processing solutions.

The AS103 is fully compliant with OpenVPX standard, accommodating various serial communication protocols in addition to the VME bus.

The AS103 combines the flexibility and ultra-high processing power delivered by the Xilinx® Kintex® Ultrascale+™ FPGA with the support of two FMC mezzanines.

The AS103 includes two 16-bit 2.5 Gsps DAC and one 16-bit 370 Msps ADC that can be used for additional analog interface.

The AS103 features an internal ultra-low jitter reference and one clock synthesizers and can be used with either external clock for higher flexibility. Both internal or external clock are routed on FMC slots allowing synchronization between FMC Boards.

The AS103 includes one Xilinx® Kintex® Ultrascale+™ KU115 FPGA for an impressive processing capability of more than 7 TMACs (Multiply Accumulate per second), one high speed 256M32 DDR3 SDRAM memory for data processing and one 1 Gb synchronous FLASH memory for multiple firmware storage.

The AS103 provides a 10/100 Ethernet interface intended to be used for system monitoring and supervision.

An FPGA Development Kit is provided including all necessary cores to build user FPGA application.

16-bit 370 Msps ADC

The AS103 Analog to Digital conversion is performed by one Texas Instrument ADC16DX370 16-bit 370 Msps ADCs. The AS103 provides one front panel SMPM connector for analog input. Single ended input signal is AC coupled with an input bandwidth from 4.5 MHz to 300 MHz with 9 dBm input level.

16-bit 2.5 Gsps DAC

The AS103 Digital to Analog conversion is performed by a Dual 16-bit 2.5 Gsps DAC with independent Digital Up Converters with interpolation factor ranging from 1 to 16. The AS103 provides two front panel SMPM connectors for analog outputs. Single ended output signals are DC coupled with an output bandwidth from 0 MHz to 500 MHz with 6 dBm output level.


The AS103 provides one ultra-low jitter clock synthesizers locked on a 100 MHz internal reference. External clock from 100 MHz to 6 GHz are supported. The AS103 provides one front panel SMPM connector for clock input An external clock output is provided on SMPM connector.

Optical transceivers

The AS103 includes one firefly optical transceiver with 12 Tx and 12 Rx optical fiber interfaces supporting up to 14Gbps per link. Optical interface is provided on MTP connector.


The AS103 is fitted with a Xilinx® Kintex® Ultrascale+™ KU115 user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR3 SDRAM and monitoring sub-system, leaving most of the logic and block RAM and all DSP resources available for customer processing. Dedicated to signal processing, the Xilinx Kintex Ultrascale KU115 FPGA includes 1,451 K logics cells, 2,160 36 Kbit RAM blocs, 6 PCIe interface blocs and 5,520 DSP48 slices for an impressive processing power of more than 7 TMACs. The FPGA is delivered in -2 speed grade.

VXS Interface

The AS103 supports VME A32 / D32 slave access with interrupt generation capabilities. CR/CSR configuration space is supported for board configuration. The AS103 features a VXS compliant interface with support of 2x 4 serial lanes up to 12.5Gbps per link. The AS103 also supports 12 LVDS differential pairs on VXS P0 plus 13 LVDS differential pairs on VME P2 plus one trigger input on VME P2.

FMC Interface

The AS103 features two VITA 57 – FMC (FPGA Mezzanine Card) compliant slots. Each FMC slot supports High Pin Count (HPC) interface with up to 80 differential signal pairs. Each FMC interface also supports 10 high-speed serial links running at up to 12.5Gbps in full duplex.


The AS103 includes one 800 MHz 256M32 DDR3 SDRAM memory banks and one 1 Gbit QSPI FLASH used to store multiple FPGA configuration files.


The AS103 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision. The microcontroller supports a 10/100 Ethernet interfaces accessible on the VME P2 user IO pins through an ApisSys AR108 Test Module. The microcontroller firmware includes all necessary features for board monitoring and supervision.


The AS103 comes with a firmware package which includes VHDL cores allowing for control and communication with all AS103 hardware resources. Base designs are provided which demonstrates the use of the AS103 and gives users a starting point for firmware development. The AS103 firmware package is supported on the Xilinx VIVADO® 2016.4 design suite.


The AS103 is delivered with software drivers for Windows and Linux (Ethernet) and VxWorks 6.9 (VME).


The AS103 is delivered in air cooled standard or rugged versions for use in severe environmental conditions. Standard VITA 47 supported ruggedization levels are EAC4 and EAC6.

AS103 - Architecture

Analog Input/Output

Input coupling: AC
Full power bandwidth: 4.5 to 300 MHz
Full scale : 9 dBm
Output Coupling: AC
Full power bandwith: 0 to 500 MHz
Full scale : 6 dBm (NRZ)
Impedance: 50 Ohms
Connectors: SMPM

Analog-Digital Conversion

One channel, Fs ≤ 370 MHz
Resolution: 16 bit
Performances @84 Msps 15 MHz Fs = 84 MHz
SNR: 67 dBFS (-3 dBFS)
SFDR: 69 dBc
ENOB: 11 bits

Digital-Analog Conversion

Two channels, Fs ≤ 2.5 GHz
Resolution: 16 bit
Performances @168 Msps 30 MHz Interpolation = 2
SFDR: 67 dBc (0 dBFs)
NSD: -145 dBm/Hz


One ultra-low jitter clock synthesizer
2 GHz to 6 GHz low jitter clock
External Input Clock:
Frequency: 100 MHz to 6 GHz
Input level: 10 dBm recommended
Connector: SMPM 50 Ohms

FMC Interface

1.8V or 1.5V VADJ, default to 1.8V
HPC: 80 differential pairs
10 serial lanes up to 12.5Gbps

Optical Transceivers

12 Tx and 12 Rx optical
Multimode 850nm fiber
Up to 14Gbps per link
Connector MTP


One bank 256M32 DDR3 SDRAM, 800 MHz clock
One 1 Gbit QSPI FLASH memory

VPX interface

VME A32 D32 Slave
VME IRQ Generation support
VME CR/CSR configuration space
VXS 8 serial lanes up to 12.5Gbps
12 LVDS pairs on VXS P0
13 LVDS pairs on VME P2


FPGA: Xilinx Kintex Ultrascale

Software support

Software Drivers:
Windows and Linux (ethernet)
VxWorks 6.9 (VME)
Application example: Windows, Linux, VxWorks

Firmware support

VHDL cores for all hardware resources
Base design
Supported by Xilinx VIVADO 2016.4


As per VITA 47:
Air cooled : EAC4 and EAC6

Power dissipation

+5V: 14.8 / 14.8 A max (74 / 74 W)
+3.3V: 6.9 / 17.7 A max (22.8 / 58.4 W)
+5V_STDBY: 0.54 A max (2.7W)
+12V: 0 / 2 A max (0 / 24 W)


Air cooled : 665g
Part Number
A S 103 - rr - a
Ruggedization level

Air Standard

Air Rugged















Options 1

FPGA Kintex Ultrascale KU115








  Air flow, Standard
AS (VITA 47 EAC4)  
Air flow, Rugged
AR (VITA 47 EAC6)  
0°C to +55°C (1)
(10 CFM airflow at sea level)
-40 to +70ºC (1)
(20 CFM airflow at sea level)
Non Operating Temperature -40°C to +85°C -50°C to +100°C
5Hz - 100Hz +3 dB/octave
100Hz-1kHz = 0.04 g2/Hz
1kHz - 2kHz -6 dB/octave
5Hz - 100Hz +3 dB/octave
100Hz - 1kHz = 0.04 g2/Hz
1kHz - 2kHz -6 dB/octave
Operating Shock 20g, 11 millisecond, half-sine 20g, 11 millisecond, half-sine
Relative Humidity
0% to 95%
0% to 95%
@ 0 to 10,000 ft
with adequate airflow
@ 0 to 30,000 ft
with adequate airflow
Conformal Coating No Optional (default acrylic AVR80)
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